1/6 preliminary data november 2000 this is preliminary data new product in development or undergoing evaluation. details are subject to change without notice. STB24NF10 n-channel 100v - 0.07 w - 24a d 2 pak low gate charge stripfet ? power mosfet n typical r ds (on) = 0.07 w n exceptional dv/dt capability n 100% avalanche tested n surface-mounting d 2 pak (to-263) power package in tape & reel (suffix at4o) description this mosfet series realized with stmicroelectronics unique stripfet process has specifically been designed to minimize input capacitance and gate charge. it is therefore suitable as primary switch in advanced high- efficiency, high-frequency isolated dc-dc converters for telecom and computer applications. it is also intended for any applications with low gate drive requirements. applications n high-efficiency dc-dc converters n ups and motor control type v dss r ds(on) i d STB24NF10 100 v <0.077 w 24 a d 2 pak to-263 (suffixat4o) 1 3 absolute maximum ratings symbol parameter value unit v ds drain-source voltage (v gs =0) 100 v v dgr drain-gate voltage (r gs =20k w ) 100 v v gs gate- source voltage 20 v i d drain current (continuos) at t c =25 c24 a i d drain current (continuos) at t c = 100 c 15 a i dm ( ? ) drain current (pulsed) 96 a p tot total dissipation at t c =25 c 80 w derating factor 0.53 w/ c dv/dt (1) peak diode recovery voltage slope 9 v/ns e as (2) single pulse avalanche energy 75 mj t stg storage temperature 65 to 175 c t j max. operating junction temperature 175 c internal schematic diagram ( ? )pulse width limited by safe operating area (2)starting tj =25 o c,i d =24a ,v dd =50v (1)i sd [ 24 a, di/dt m 300a/ms, v dd [ v (br)dss ,tj [ t jma
STB24NF10 2/6 thermal data electrical characteristics (t case =25 c unless otherwise specified) off on (* ) dynamic r thj-case thermal resistance junction-case max max 1.87 c/w r thj-amb thermal resistance junction-ambient max max 62.5 c/w t j maximum lead temperature for soldering purpose 300 c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 m av gs = 0 100 v i dss zero gate voltage drain current (v gs =0) v ds = max rating v ds = max rating, t c = 125 c 1 10 m a m a i gss gate-body leakage current (v ds =0) v gs = 20 v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds =v gs i d = 250 m a234v r ds(on) static drain-source on resistance v gs =10v i d = 12 a 0.07 0.077 w w i d(on) on state drain current v ds >i d(on) xr ds(on)max v gs =10v 24 a symbol parameter test conditions min. typ. max. unit g fs (*) forward transconductance v ds >i d(on) xr ds(on)max i d =12 a 20 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitances v ds = 25v f = 1 mhz v gs = 0 870 125 52 pf pf pf
3/6 STB24NF10 switching on switching off source drain diode (*) pulsed: pulse duration = 300 m s, duty cycle 1.5 %. ( ? ) pulse width limit ed by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 50v i d =12a r g = 4.7 w v gs =10v (see test circuit, figure 3) 58 45 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =80vi d =24av gs =10v 30 6 10 nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd =27v i d =12a r g = 4.7 w v gs =10v (resistive load, see fig.3) 49 17 ns ns t d(off) t f t c off-voltage rise time fall time cross-over time v clamp =80v i d =24a r g = 4.7 w v gs =10v (inductive load, see fig.5) 43 36 39 ns ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm ( ? ) source-drain current source-drain current (pulsed) 24 96 a a v sd (*) forward on voltage i sd =24a v gs = 0 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd =24 a di/dt = 100 a/ m s v dd =50v t j = 150 c (see test circuit, figure 5) 100 375 7.5 ns nc a electrical characteristics (continued) ..
STB24NF10 4/6 fig. 1: unclamped inductive load test circuit fig. 1: unclamped inductive load test circuit fig. 2: unclamped inductive waveform fig. 3: switching times test circuits for resistive load fig. 4: gate charge test circuit fig. 5: test circuit for inductive load switching and diode recovery times
5/6 STB24NF10 d 2 pak mechanical data dim. mm. inch min. typ max. min. typ. max. a 4.4 4.6 0.173 0.181 a1 2.49 2.69 0.098 0.106 a2 0.03 0.23 0.001 0.009 b 0.7 0.93 0.027 0.036 b2 1.14 1.7 0.044 0.067 c 0.45 0.6 0.017 0.023 c2 1.23 1.36 0.048 0.053 d 8.95 9.35 0.352 0.368 d1 8 0.315 e 10 10.4 0.393 e1 8.5 0.334 g 4.88 5.28 0.192 0.208 l 15 15.85 0.590 0.625 l2 1.27 1.4 0.050 0.055 l3 1.4 1.75 0.055 0.068 m 2.4 3.2 0.094 0.126 r 0.4 0.015 v2 0? 8?
STB24NF10 6/6 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http://w ww.st.com
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